`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/06/2021 07:30:39 PM
// Design Name: 
// Module Name: lighter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module lighter(
    input clk,
    input rst,
    input en,
    output reg [7:0] led
    );
    parameter 
    S0 = 4'b0000,
    S1 = 4'b0001,
    S2 = 4'b0010,
    S3 = 4'b0011,
    S4 = 4'b0100,
    S5 = 4'b0101,
    S6 = 4'b0110,
    S7 = 4'b0111,
    S8 = 4'b1000,
    S9 = 4'b1001,
    CNT_NUM=10000000,
    CNT_WHOLE = 500000000;
    reg [3:0] cstate,nstate;
    reg isEnabled;
    reg [40:0] counter,count_whole;
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            isEnabled <= 0;
        end
        else
            if (en) begin
                isEnabled <= 1;
            end
            else if (count_whole == CNT_WHOLE-1) begin
                isEnabled <= 0;
            end
    end
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            counter <= 0;
        end
        else if (counter == CNT_NUM-1) begin
            counter <= 0;
        end
        else begin
            counter <= counter + 1;
        end
    end

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            count_whole <= 0;
        end
        else if (count_whole == CNT_WHOLE-1) begin
            count_whole <= 0;
        end
        else if (isEnabled)
            count_whole <= count_whole + 1;
        
    end
    assign clk2Hz = (counter==CNT_NUM-1)?1:0;
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            cstate <= S0;
        end
        else
            cstate <= nstate;
    end

    always @(*) begin
        if(clk2Hz && isEnabled)
            case (cstate)
                S0:nstate = S1;
                S1:nstate = S2;
                S2:nstate = S3;
                S3:nstate = S4;
                S4:nstate = S5;
                S5:nstate = S6;
                S6:nstate = S7;
                S7:nstate = S8;
                S8:nstate = S9;
                S9:nstate = S0;
                default: nstate = S0;
            endcase
        else nstate = cstate;
    end

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            led <= 8'b00000000;
        end
        else if(isEnabled)
            case (cstate)
                S0:led <= 8'b00000000;
                S1:led <= 8'b10000001;
                S2:led <= 8'b11000011;
                S3:led <= 8'b11100111;
                S4:led <= 8'b11111111;
                S5:led <= 8'b00000000;
                S6:led <= 8'b00011000;
                S7:led <= 8'b00111100;
                S8:led <= 8'b01111110;
                S9:led <= 8'b11111111; 
                default: led <= 8'b00000000;
            endcase
    end

endmodule
